USA

I build systems that fail safely.

Functional Safety Engineer specializing in ISO 26262, ASIL-D systems, autonomous driving, and MCU and semiconductor safety integration.

  • 5+ years in Functional Safety
  • ASIL A–D programs
  • ISO 26262 lifecycle ownership
  • Safety Cases
  • MCU safety mechanism integration
  • HARA · FSC · TSC · FMEDA · FTA
Professional experience

I spend most of my working hours thinking about the ways things go wrong. Not because I'm pessimistic — because in my field, someone has to be. I'm a Functional Safety Engineer, and for the past five years I've worked on the systems that are supposed to fail quietly, predictably, and never at the worst possible moment.

Across that work, I've achieved the random hardware failure metrics — SPFM, LFM, and PMHF — required to meet ASIL-A through ASIL-D targets per ISO 26262, on systems ranging from restraint control to autonomous driving features.

Right now that includes airbags. At a Tier 1 automotive supplier, I own the full safety story of a Restraint Control System, from the first hazard we identify on paper to the safety case we hand over at the end — the document that says, with evidence, this will do what it's supposed to do, even when something inside it breaks. That's the promise of ASIL-D, the highest integrity level in automotive safety, and getting there means tracing every requirement back to a hazard, every safety mechanism back to a failure mode, until nothing is left unaccounted for. The safety case itself reports how much of that requirement set is actually covered by evidence — and wherever something isn't, I don't leave a gap. I run a risk assessment on it and fold that in as evidence that the residual risk is understood and acceptable.

"Getting to ASIL-D means tracing every requirement back to a hazard — until nothing is left unaccounted for."

My safety work spans the active side too — cars that could see and decide. On earlier OEM and Tier 1 programs, I worked on the safety case for autonomous driving features — lane centering, automated parking, adaptive cruise control — systems that have to make a judgment call every few milliseconds about what's safe to do next. That work taught me something the restraint systems hadn't: safety isn't just about hardware failing gracefully. It's about a system correctly reading the world and knowing when not to act.

Earlier still, on Tier 1 supplier programs, I was the person in the room translating a new feature — a digital mirror, a power window, a clutch actuator — into a hazard analysis, a safety concept, a set of requirements a supplier could actually build against. One of my safety specifications shipped a week ahead of schedule, and I was recognized by the OEM as one of the top-performing engineers among more than eighty engineers on the program.

Professional experience

A safety goal stays abstract until someone decides which microcontroller will execute the function, what that device can actually detect about its own failures, and what it quietly assumes the rest of the ECU will handle. Much of my work sits exactly there.

For a candidate MCU, that means working through the safety manual: which failure modes the vendor's safety mechanisms really cover across the CPU, memories, DMA, watchdogs, clock monitoring, communication interfaces, and other peripherals, and under which assumptions of use. Where a mechanism is not implemented, does not apply to our configuration, or is not strong enough for the target, I work out what has to compensate at the system level, and what diagnostic coverage and residual risk that leaves behind.

The same discipline applies beyond the MCU. Evaluating a safety-related pressure sensor means looking at its diagnostics, the plausibility checks the ECU can apply, and the sensor-to-MCU communication path as one chain rather than separate parts. And the supplier relationship is part of the engineering: development interface agreements, supplier safety documentation, and Safety Element out of Context assumptions decide who is responsible for verifying what.

Independent study

Working at that boundary changed which questions I ask. A safety manual says a lockstep core detects certain faults with a stated coverage, or that a memory is protected by ECC, and I build an ECU safety argument on those statements. I want to understand what stands behind them: how the logic is actually structured, how a fault in a register or a bus propagates, and what evidence a silicon vendor would need to substantiate a diagnostic coverage claim.

Understanding how a safety-critical ECU behaves during failure requires understanding the semiconductor devices inside it. That is why I'm studying digital logic and RTL, microcontroller architecture, ISO 26262 Part 11, and fault injection.

Digital electronics and RTL

CMOS and transistor behavior, logic gates, combinational and sequential logic, flip-flops, registers, finite-state machines, Verilog and VHDL, RTL simulation, synthesis, and FPGA implementation.

Semiconductor architecture

ARM Cortex-based microcontrollers, lockstep and self-test, SRAM, Flash and ECC, DMA, SPI, ADC paths, clock and voltage supervision, safety management units, and watchdogs.

Semiconductor safety analysis

Part 11 concepts, IP-level and device-level FMEDA, failure-rate and failure-mode distribution, diagnostic coverage justification, package-level failures, and dependent failures.

Safety verification

Stuck-at and transient faults, fault injection and observation, safety mechanism effectiveness, detection latency, and the link between verification evidence and FMEDA assumptions.

To be precise about where this stands: this is study and independent engineering exploration. I have not held a semiconductor design or verification role, and I don't present any of it as professional ASIC or silicon experience.

My work sits across four connected domains. Vehicle- and system-level functional safety defines what must be achieved and how it is allocated. At the ECU level, software and hardware safety are parallel branches that implement it together. Semiconductor safety is a deeper level of abstraction: the devices those ECUs are built on. Reaching it is a matter of supplier integration and technical curiosity, not a phase that follows ECU development.

Professional experience and independent study are marked separately throughout. Select a domain to open it.

Professional experience Independent study Owned Owned / Co-owned Familiar reviewed or contributed Study independent study

Part references follow ISO 26262:2018. The Work Products page maps each part to these domains in more detail.

01Vehicle and System Functional SafetyProfessional experience

Two levels of abstraction. At the vehicle level, the concept phase defines the item, assesses its hazardous events as they affect the vehicle, and sets the safety goals and the functional safety concept. At the system level, the technical safety concept turns those into technical requirements allocated to the system design, followed by integration and safety validation. Everything in the other three domains traces back to this one.

Vehicle level — concept phase ISO 26262-3

  • Item definitionOwned
  • Hazard analysis and risk assessment (HARA)Owned
  • Hazardous events and ASIL determinationOwned
  • Safety goalsOwned
  • Functional safety concept (FSC)Owned
  • Functional safety requirements (FSRs)Owned

System level — product development ISO 26262-4

  • Technical safety concept (TSC)Owned
  • Technical safety requirements (TSRs)Owned
  • System architectureOwned
  • Safety requirements allocationOwned
  • Safety mechanisms and diagnostic strategiesOwned
  • System integration and verificationContributed to verification reports; did not own vehicle-level validation.Familiar
  • Safety analysis and dependent failure considerationsOwned
02ECU Software Functional SafetySpecification and analysisTechnical knowledge

How the software on an ECU is specified, partitioned, and supervised so that it detects faults and reacts to them. My experience is in specifying, analyzing, and integrating software-related safety mechanisms into the ECU safety concept. It is not hands-on embedded software implementation.

Software safety ISO 26262-6

  • Software safety requirementsAuthored as part of feature-level safety work products.Owned
  • Software architecture and safety mechanismsReviewed for safety-relevant partitioning; software design not authored.Familiar
  • Software–hardware interfaceFamiliar
  • Watchdog servicing and supervisionSpecified and analyzed as a safety mechanism.Owned
  • Runtime monitoringStudy
  • Memory and program-flow monitoringFamiliar
  • Communication protection and end-to-end data integritySpecified and analyzed as a safety mechanism.Owned
  • Software diagnostic handlingOwned
  • Fault reaction and safe-state transitionsSpecified as part of the technical safety concept.Owned
  • Software safety verificationContributed to verification reports; did not execute unit test suites.Familiar
  • Embedded software coding and implementationNot part of my professional experience.None

“Owned” in this domain means specified, analyzed, or integrated as requirements and mechanisms at the ECU level. I have not implemented these mechanisms in code.

03ECU Hardware Functional SafetyProfessional experience

Where safety goals become hardware-level guarantees: diagnostic coverage, quantified residual risk, and the signal paths between sensors and the MCU. This is the area closest to my day-to-day work, and where semiconductor supplier integration happens.

Hardware safety ISO 26262-5

  • Hardware safety requirementsOwned
  • ECU hardware architectureSafety analysis of the architecture; circuit-level design not authored.Owned
  • Hardware FMEA and FMEDAOwned
  • Fault tree analysis (FTA)Owned
  • SPFM, LFM and PMHFOwned
  • Random hardware failure analysisOwned
  • Diagnostic coverage assessmentOwned
  • Power supply monitoringOwned
  • Sensor interface safetyIncluding diagnostics and plausibility checks on the sensor-to-MCU path.Owned
  • MCU peripheral diagnosticsOwned
  • SPI communication integrityOwned
  • Watchdogs and external monitoring circuitsOwned
  • Hardware safety mechanism integrationOwned
  • Supplier safety manual evaluationOwned
  • Hardware safety verificationContributed to verification reports.Familiar
04Semiconductor Functional SafetyProfessional MCU integrationIndependent study

The devices inside the ECU. This is a deeper level of abstraction, reached through supplier integration and curiosity, not a phase that follows ECU development. Professionally I work at the integrator side of this boundary. Everything from digital logic downward is independent study.

Guidance ISO 26262-11, with Parts 5 and 6

ASemiconductor Safety ArchitectureProfessional integrationDevice-level: study

“Owned” here means evaluated and integrated as an integrator at the ECU level. I have not designed these mechanisms.

  • MCU safety architectureOwned
  • CPU lockstepOwned
  • ECC and memory protectionOwned
  • DMA safetyOwned
  • Clock monitoringOwned
  • SMU and fault managementStudy
  • WatchdogsOwned
  • Peripheral safety mechanismsOwned
  • Semiconductor safety manualsOwned
  • Assumptions of Use (AoUs)Owned
  • Semiconductor FMEDA and dependent failure analysisDevice-level analysis is study; the integrator-side FMEDA is in domain 03.Study
BDigital Logic FundamentalsIndependent study
  • CMOSStudy
  • Logic gatesStudy
  • Combinational logicStudy
  • Sequential logicStudy
  • Flip-flops and registersStudy
  • Finite-state machinesStudy
CRTL Design and VerificationIndependent study

Planned through the engineering explorations. No completed work yet.

  • Verilog / SystemVerilogStudy
  • RTL simulationStudy
  • Safety mechanism implementation conceptsStudy
  • Fault injectionStudy
  • Diagnostic coverage evaluationStudy
  • RTL safety verificationStudy
DSemiconductor Physical ImplementationIndependent study
  • Logic synthesisStudy
  • Gate-level netlistsStudy
  • Place and routeStudy
  • Static timing analysisStudy
  • Physical failure mechanismsStudy
  • Semiconductor reliabilityStudy
  • Physical implementation considerationsStudy

Not part of my experience: RTL design, ASIC verification, or physical design roles. These are subjects I'm studying and intend to demonstrate through independent projects.

Independent study

To turn study into evidence, I've defined five independent projects. All five are proposed; none is completed, and none has results yet. Each one states its safety problem, its method, and the evidence it would produce, so the page can grow with diagrams, HDL, waveforms, and repositories as they exist.

  1. RTL Safety Mechanism Exploration Proposed
  2. DMA Data Integrity and Safety Proposed
  3. Fault Injection and Diagnostic Coverage Proposed
  4. MCU Safety Mechanism Integration Framework Proposed
  5. Fault Tolerant Time Interval (FTTI) Exploration Proposed
Read the explorations →

"How do we prove a system remains safe when the unexpected happens?"

I believe the future of engineering is not simply making systems more intelligent, but making them trustworthy. As vehicles, robots, and AI systems become increasingly autonomous, safety must evolve from verifying components to validating decisions. My work is driven by one question: how do we prove a system remains safe when the unexpected happens?

My experience today is rooted in ISO 26262 for automotive safety, and in the MCU and semiconductor integration that sits underneath it. Closer in, I'm building deeper competence in semiconductor functional safety, RTL design, and hardware safety verification. Further out, I'm increasingly interested in how these principles extend to robotics and AI systems, where the challenge shifts from proving deterministic behavior to building confidence in systems that learn, adapt, and interact with the physical world.

Portrait of Bharath Kumar Bahunuthula

Bharath Kumar Bahunuthula

Find the hazard, trace it to the fix,
and prove the system is safe.

Availability limited to two weekend slots